The present invention relates to a technique for use in the manufacture of a semiconductor device; and, more particularly the invention relates to a technique which is effective when applied to manufacturing steps in which a semiconductor wafer, having an adhesive tape adhered thereto, is divided into a plurality of semiconductor chips by dicing, and, thereafter, the respective semiconductor chips are peeled from the adhesive tape.
Recently, with the objective of achieving high-density packaging of a semiconductor device, a stacked package in which plural sheets of semiconductor chips are three-dimensionally mounted on a printed wiring board has been put into practice. However, in assembling such a stacked package, the semiconductor chips (hereinafter, simply referred to as “chips”) which are used are processed such that the thickness of the each chips is reduced to approximately several tens μm.
In mounting such thin chips on a printed wiring board, first of all, on a main surface of a semiconductor wafer (hereinafter, simply referred to as “wafer”) on which a desired integrated circuit is formed, a tape which protects the integrated circuit is laminated. In such a state, by polishing or etching a rear surface of the wafer, the thickness of the wafer is decreased to approximately several tens μm. Then, dicing is performed, in a state in which adhesive tape is laminated to the rear surface of the thin wafer, so as to divide the wafer into a plurality of chips. Thereafter, the rear surface of the adhesive tape is pushed up by pusher pins and the like to peel the chips one after another from the adhesive tape. The peeled chips are picked up by a collet and are transported to the printed wiring board where pellet-bonding is performed.
Here, in the abovementioned package assembling steps which use extremely thin chips, when the chips which are divided by dicing are peeled or are picked up from the adhesive tape, cracks or chippings are liable to easily occur on the chips; and, hence, it is necessary to provide measures to prevent the occurrence of these cracks or chippings.
Japanese Unexamined Patent Publication Hei 6(1994)-295930 discloses a technique which prevents the occurrence of cracks and chippings when the chips are peeled from the adhesive tape. A chip peeling device, as described in the literature, includes a support base which supports an adhesive sheet to which a wafer which is divided into a plurality of chips is adhered, a peeling head which is arranged below the support base, peeling pins which are housed in the inside of the peeling head and are constituted of slide pins which rub a back surface of the adhesive sheet and pusher pins which push up the chips, and drive means which move the slide pins and the pusher pins, respectively, in the horizontal direction and in the vertical direction.
In peeling the chips from the adhesive sheet using the abovementioned chip peeling device, first of all, the slide pins are brought into contact with back surfaces of portions of the adhesive sheet to which the chips to be peeled are adhered; and, thereafter, the slide pins are made to rub the sheet surface, while being reciprocated in the horizontal direction, so that the adhesive strength between the adhesive sheet and the chips is weakened. Next, by elevating the slide pins and the pusher pins simultaneously so as to lift the chips, the chips having a weakened adhesive strength relative to the adhesive sheet are peeled from the adhesive sheet without requiring a strong pushing force.
[Patent Document]
Japanese Unexamined Patent Publication No. Hei 6(1994)-295930